1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a static random access memory (SRAM).
2. Description of the Related Art
With the recent progress in the fine patterning technology and the demand for improved system performance, more and more semiconductor memory devices having large storage capacity and operating at high speed are developed. FIG. 8 is a circuit diagram illustrating an example of an SRAM.
Referring to FIG. 8, a plurality of memory cells MC are arranged in a column direction which a bit line extends to. The memory cells MC are divided into a plurality of sub-arrays, each including a predetermined number of memory cells MC. Word lines WL and a pair of local bit lines LBL and /LBL are provided for each sub-array. In each sub-array, the memory cells are connected to the local bit lines LBL and /LBL and the corresponding ones of the word lines WL. A write circuit and a pre-charge circuit are connected to the local bit lines LBL and /LBL. A pair of global bit lines WGBL and /WGBL used for writing are connected to the write circuit. Local bit line LBL is connected to the read circuit, which in turn is connected to global bit line RGBL used for reading.
In the SRAM having the above configuration, the read circuit is connected only to the local bit line LBL. This single-end read circuit is advantageous in that it helps reduce the number of global bit lines required. In general, if the capacitance load on the bit lines, which are due to the capacitance of memory cells and the wiring capacitance, increases, the read operation is inevitably low in speed. However, if the local bit lines are provided in layers as in the SRAM shown in FIG. 8, the capacitance load on the bit lines can be reduced.
To access the SRAM, word lines are activated. In general, the pre-charging operation is stopped for the local bit lines of the sub-arrays for which the pre-charging operation is performed until then and which includes the activated word lines. This selective pre-charging operation is accomplished by selecting areas of the corresponding sub-arrays on the basis of address signals entered for the activation of the word lines.
In practice, however, there may be a case where this area selection cannot be performed. Also, there may be a case where signals for selecting the areas are too slow for the SRAM to wait for. An example of an apparatus where this problem occurs is a translation lookaside buffer (TLB) wherein a content address memory (CAM) and an SRAM are connected together. The CAM and the SRAM are connected together by means of a plurality of matching lines. In the TLB, word lines WL are selected by activation signals which the CAM generates on the basis of address signals. Signals used for selecting areas must be generated by use of the matching lines. Therefore, the area selection signals are generated after the activation signals used for selecting word lines are generated. In other words, the SRAM cannot operate until the area selection signals are generated or determined. As a result, a long time is required before data is output.
To solve this problem, it may be thought not to perform the pre-charging operation for all local bit lines for which the pre-charging operation is performed until then, irrespective of whether there are word lines that are activated. If this measure is taken, the local bit lines of the areas where the word lines are not activated, are set in the so-called “floating high state.” The floating high state is a state where power source voltage Vcc first applied, raising the potential level to high, and then the application of the power source voltage Vcc stops. If this phenomenon occurs, leak current increases especially in miniaturized transistors. In addition, the leak current from a local bit line may increase if many transistors (which are likely to be leak current sources) are connected to that local bit line. If the leak current is too large in amount, a high potential level cannot be maintained in the floating high state, and the potential level of the local bit lines drops to low, resulting in a malfunction or an undesirable phenomenon.
To prevent this malfunction or undesirable phenomenon, it is thought to add a P-type MOS transistor and connect this transistor to the local bit lines to maintain a high potential state. FIG. 9 is a circuit diagram illustrating an example of a circuit to which such a P-type MOS transistor is added. However, an SRAM having this configuration does not function well because the addition of the P-type MOS transistor conflicts with the operation of reading memory cells at low level. As a result, the read operation will be slow.
As a relevant technology, Jpn. Pat. Appln. KOKAI Publication No. 4-167295 discloses how to prevent read data from becoming indefinite when an address signal does not select any of the word lines.